View CHK040A-SOA26_8045711.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 1 / 14 specifications subject to change without notice united monolithic semiconductors s.a.s. bat. charm ille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel .: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 40w power packaged transistor gan hemt on sic description the chk040a - soa is an unmatched p ackaged gallium nitride high electron mobility transistor. it offers general purpose and broadband solution s for a variety of rf power applications. it is well suited for multi - purpose applications such as radar and telecommunica tion the chk040a - soa is developed on a 0.5m gate length gan hemt process . it requires an external matching circuitry . the chk040a - soa is available in a ceramic - metal flange power package providing lo w par asitic and low thermal resistance . main features v ds = 50v, i d_q = 3 00ma, freq= 3 ghz pulsed mode intrinsic performances of the packaged device ds =50v @ i d_q =300ma 6 hours @ tj=200c main electrical characteristics tcase = + 25c , p ulsed mode , f = 3 ghz , v d s =50v, i d _ q =30 0ma symbol parameter min typ max unit g ss small signal gain 16 1 8 - db p sat saturated output power 45 55 - w pae max power added efficiency 55 6 0 - % g pae_max associated gain at max pae 13 - db pout pae id gain 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 0 5 10 15 20 25 30 35 40 45 50 55 60 12 14 16 18 20 22 24 26 28 30 32 34 36 38 id (a) gain (db), pout (dbm) & pae (%) input power (dbm) pulsed mode at 3ghz
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 2 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended dc operating ratings tcase= +25c symbol parameter min typ max unit conditions v ds drain to source voltage 20 50 v v gs_q gate to source voltage - 1.8 v v d =50v, i d_q = 3 00ma i d_q quiescent drain current 0. 3 1 a v d =50v i d _max drain current 2 (1) a v d =50v, c ompressed mode i g_max gate current (forward mode) 0 2 4 ma compressed mode t j _max junction temperature 200 c (1) limited by dissipated power dc characteristics tcase = +25c symbol parameter min typ max unit conditions v p pinch - off voltage - 3 - 2 - 1 v v d =50v, i d = i dss /100 i d_sat saturated drain current 8 (1) a v d =7v, v g = 2 v i g_leak gate leakage current (reverse mode) - 3 m a v d =50v, v g = - 7v v bds drain - source break - down voltage 200 v v g = - 7v, i d =20ma r th thermal resistance 2.85 c/w (1) for information, limited by i d _max , s ee on absolute maximum ratings rf characteristics (cw) tcase= +25c, cw mode , f = 3ghz , v ds =50v, i d_q =300ma symbol parameter min typ max unit g ss small signal gain 15 17 - db p sat saturated output power 40 50 - w pae max power added efficiency 50 55 - % g pae_max associated gain at max pae 12 - db
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 3 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 rf characteristics ( p ulsed) tcase= +25c, pulse mode (1) , f = 3ghz , v ds =50v, i d_q =300ma symbol parameter min typ max unit g ss small signal gain 16 1 8 db p sat saturated output power 45 55 w pae max power added efficiency 55 6 0 % g pae_max associated gain at max pae 13 db (1) input rf and gate voltage are pulsed. c onditions are 25s wid th, 10% duty cycle and 1s offset between dc and r f pulse. these values are the intrinsic performance of the packaged device. they are deduced from measurements and simulations. they are considered in the reference plane defined by the leads of the package, at the connection interface with the pcb. the typical pe rformance achievable in more than 25% frequency band around 3ghz was demonstrated using the reference board 61499547 presented hereafter. absolute maximum ratings tcase = +25c (1) , (2), (3) symbol parameter rating unit note v ds drain - source voltage 60 v v gs _q gate - source voltage - 10, +2 v (6) i g _ max maximum gate current in forward mode 7 2 ma i g _ m in maximum gate current in reverse mode - 12 ma i d_ max maximum drain current 6 a (4) p in maximum input power (typical) 3 9 dbm (5) t j junction temperature 220 c t stg storage temperature - 55 to +150 c t c ase case operating temperature see note c (4) ( 1) operation of this device above anyone of these parameters may cause permanent damage. (2) duration < 1s. (3 ) the given values must not be exceeded at the same time even momentarily for any parameter, since each parameter is independent from each other, otherwise deterioration or destruction of the device may take place. (4) max junction temperature must be considered (5) @ 3ghz - linked to and limited by i g_max & i g_min values (6) v gs _q max limited by i d _max and i g _ max values
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 4 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 simulated source and load impedance v ds = 50v, i d_q = 3 00ma frequency (mhz) source load 500 1 + j 4. 5 21.6 + j 7 1000 1 + j 1. 9 15.3 + j1 4.3 2000 1.3 - j 1.9 5 + j7. 9 3000 1.4 - j 4.8 2.8 + j 2.3 3500 0.8 - j 6.7 2. 3 + j0. 2 these values are given in the reference plane defined by the connection between the package leads and the pcb. a gap of 200m is considered between the edge of the package and the pcb . zload zsource
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 5 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical s - parameters tcase= +25c, cw mode, v d =50v, i d_q =300ma , phase s(i,j) in freq (ghz) mag s(1,1) p hase s(1,1) m ag s(2,1) p hase s(2,1) m ag s(1,2) p hase s(1,2) m ag s(2,2) p hase s(2,2) 0 0.99 0.00 102.98 - 180.00 0.0000 180.00 0.53 0.00 0.25 0.89 - 148.78 26.70 94.89 0.0120 8.67 0.37 - 127.84 0.5 0.90 - 165.08 13.34 77.63 0.0120 - 4.55 0.42 - 137.95 0.75 0.90 - 171.34 8.59 65.80 0.0110 - 11.66 0.50 - 141.46 1 0.91 - 175.14 6.13 55.96 0.0090 - 15.55 0.57 - 144.97 1.25 0.92 - 178.05 4.64 47.41 0.0080 - 16.10 0.63 - 148.80 1.5 0.93 179.44 3.65 39.85 0.0060 - 12.17 0.69 - 152.71 1.75 0.93 177.13 2.95 33.12 0.0050 - 2.19 0.73 - 156.53 2 0.94 174.95 2.45 27.06 0.0050 13.92 0.77 - 160.17 2.25 0.94 172.84 2.06 21.58 0.0050 31.44 0.80 - 163.60 2.5 0.95 170.78 1.77 16.56 0.0060 44.67 0.82 - 166.83 2.75 0.95 168.74 1.54 11.94 0.0070 52.66 0.84 - 169.87 3 0.95 166.71 1.36 7.63 0.0080 56.95 0.86 - 172.76 3.25 0.95 164.67 1.22 3.58 0.0100 58.94 0.87 - 175.50 3.5 0.95 162.61 1.10 - 0.26 0.0120 59.51 0.88 - 178.13 3.75 0.95 160.53 1.00 - 3.92 0.0130 59.18 0.89 179.33 4 0.96 158.40 0.93 - 7.46 0.0150 58.27 0.90 176.87 4.25 0.95 156.21 0.86 - 10.90 0.0170 56.96 0.90 174.46 4.5 0.95 153.96 0.81 - 14.26 0.0190 55.36 0.91 172.08 4.75 0.95 151.63 0.76 - 17.59 0.0200 53.56 0.91 169.73 5 0.95 149.21 0.73 - 20.90 0.0220 51.60 0.92 167.39 5.25 0.95 146.67 0.70 - 24.22 0.0240 49.50 0.92 165.04 5.5 0.95 144.01 0.68 - 27.57 0.0270 47.28 0.92 162.66 5.75 0.95 141.19 0.66 - 30.99 0.0290 44.94 0.92 160.25 6 0.94 138.20 0.65 - 34.51 0.0310 42.48 0.92 157.78 6.25 0.94 134.99 0.64 - 38.14 0.0340 39.89 0.92 155.24 6.5 0.93 131.54 0.64 - 41.93 0.0370 37.14 0.92 152.61 6.75 0.93 127.81 0.64 - 45.92 0.0400 34.22 0.92 149.87 7 0.92 123.74 0.65 - 50.14 0.0430 31.10 0.92 146.99 7.25 0.92 119.28 0.66 - 54.64 0.0470 27.73 0.91 143.95 7.5 0.91 114.35 0.68 - 59.48 0.0510 24.07 0.91 140.70 7.75 0.90 108.86 0.70 - 64.72 0.0550 20.05 0.91 137.23 8 0.89 102.71 0.73 - 70.44 0.0610 15.61 0.90 133.46 8.25 0.88 95.78 0.76 - 76.71 0.0660 10.66 0.90 129.35 8.5 0.87 87.92 0.80 - 83.64 0.0730 5.10 0.89 124.82 8.75 0.85 78.95 0.84 - 91.33 0.0800 - 1.18 0.89 119.78 9 0.83 68.71 0.89 - 99.89 0.0880 - 8.30 0.88 114.10 9.25 0.82 57.03 0.95 - 109.45 0.0970 - 16.37 0.87 107.63 9.5 0.80 43.79 1.00 - 120.09 0.1060 - 25.51 0.87 100.14 9.75 0.79 28.98 1.05 - 131.91 0.1150 - 35.83 0.86 91.38 10 0.78 12.80 1.10 - 144.94 0.1230 - 47.36 0.85 81.00
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 6 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 maximum gain & stability characteristics tcase= +25c, cw mode, v d =50v, i d_q =300ma 0.0 1.0 2.0 3.0 4.0 0 5 10 15 20 25 30 35 40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 k factor max. gain (db) frequency (ghz) maximum gain k factor
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 7 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical performance on demonstration board (ref. 61499547) calibration and measurements are done on the connector reference accesses of the demonstration boards. tcase = +25c, cw mode measured id, pout, gain & pae f = 3ghz, v ds = 50v, i d_q = 300ma measured gain, pout & pae pin = 38dbm, v ds = 50v, i d_q = 300ma 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 0 5 10 15 20 25 30 35 40 45 50 55 14 16 18 20 22 24 26 28 30 32 34 36 38 40 id (a) gain (db), pout (dbm) & pae (%) input power (dbm) cw mode at 3ghz pae pout id gain 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 32 34 36 38 40 42 44 46 48 50 52 54 56 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 gain (db) pout (dbm) & pae (%) frequency (ghz) cw mode pae pout gain
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 8 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 typical performance on demonstration board (ref. 61499547) calibration and measurements are done on the connector reference accesses of the demonstration boards tcase = +25c, pulsed mode (1) measured id, pout, gain & pae f = 3ghz, v ds = 50v, i d_q = 300ma measured gain, pout & pae pin = 3 8 dbm, v ds = 50v, i d_q = 300ma (1) input rf and gate voltage are pulsed. c onditions are 25s wid th, 10% duty cycle and 1s offset between dc and r f pulse. 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 0 5 10 15 20 25 30 35 40 45 50 55 14 16 18 20 22 24 26 28 30 32 34 36 38 40 id (a) gain (db), pout (dbm) & pae (%) input power (dbm) pulsed mode at 3ghz pae pout id gain 6 7 8 9 10 11 12 13 14 15 16 17 18 19 30 32 34 36 38 40 42 44 46 48 50 52 54 56 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 gain (db) pout (dbm) & pae (%) frequency (ghz) pulsed mode pae pout gain
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 9 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 demonstration amplifier low frequency equivalent schematic (ref. 61499547) demonstration amplifier / bill of materials (ref. 61499547) designator type value - description qty c1 capacitor 1.5 pf, +/ - 0. 1 pf, 0603 1 c2 capacitor 2.7 pf, +/ - 0. 1 pf, 0603 1 c3 capacitor 8.2pf, +/ - 0.25%, 0603 3 c4 capacitor 82pf, +/ - 5%, 0603 3 c 5 capacitor 240p f, +/ - 5%, 0805 3 c6 capacitor 1n f, +/ - 5%, 0805 3 c7 capacitor 10nf, +/ - 5%, 0805 3 c8 capacitor 1f, +/ - 10%, 1204 2 r1 resistor 90.9 ?, +/ ? +/ j 2 j 3 vg vd + +
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 10 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 demonstration amplifier circuit (ref. 61499547)
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 11 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 package outline ( a ) tcase locates the reference point used to monitor the device temperature. this point has been taken at the device / system interface to ease system thermal design. chamfered lead indicates the gate access of the packaged transistor. tcase (a ) (c) tcase (a ) (c) all dimensions are in mm
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 12 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended assembly procedure chk040a - soa is available has a flange package to be bolt down onto a thermal heat sink also used as main electrical ground. use preferably screw m2 and flat washers. thermal and electrical resistance at the package to heat sink interface has to be as low as possible. thermal electrically conductive grease or conductive thin layer like indium sheets are recomm ended between the package and the heat sink. in case a thermal grease is selected, we recommend to use material offering thermal conductivity >5w/m.k and electrical resistivity <0.01 ohm.cm. the grease layer thickness should be about 25m (1 mil). contact interface quality can be improved by cleaning process prior device mounting on the heat - sink. such operation will enhance the thermal and electrical contact by oxide removal at each interface. package leads can be soldered on printed circuit boards traces
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 13 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 notes
40w power packaged transistor chk040a - soa ref. : dschk040asoa3021 - 21 jan 13 14 / 14 specifications subject to change without notice bat. charmille - parc silic - 10, avenue du qubec - 91 140 villebon - sur - yvette - france tel.: +33 (0) 1 69 86 32 00 - fax: +33 (0) 1 69 86 34 34 recommended environmental management ums products are compliant with the regulation in particular with the directives rohs n2011/65 and reach n1907/2006. more environmental data are available in the application note an0019 also available at http://www.ums - gaas.com . recommended esd management refer to the application note an0020 available at http://www.ums - gaas.com for esd sensitivity and handling recommendations for the ums package products. ordering information package: chk040a - soa /xy tray : xy = 26 information furnished is believed to be accurate and reliable. however united monolithic semiconductors s.a.s. assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent righ ts of united monolithic semiconductors s.a.s. . specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. united monolithic semiconductors s.a.s. products are not authorised for use as critical components in life support devices or systems without express written approval from united monolithic semiconductors s.a.s.

▲Up To Search▲

Price & Availability of CHK040A-SOA26

	To Download CHK040A-SOA26 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .